1. Technical Field
The present invention relates to an apparatus for data processing in general and, in particular, to an apparatus for receiving data within a computer network. Still more particularly, the present invention relates to an adaptor for receiving and processing Asynchronous Transfer Mode cells within a computer network.
2. Description of the Prior Art
The transmitting and receiving of data within a computer network is well known in the art. A typical computer network consists of at least one server computer and at least one client computer. The server computer is connected to the client computer via various communications media. These communications media may include, for example, telephone lines, channels, satellites, etc. By entering a request at the client computer, a user may extract information from the server computer. Similarly, a user may enter information on the client computer and have the information transmitted to the server computer and/or to another client computer on the computer network.
Within the computer network, information is typically transmitted and received in the form of data packets. In essence, a sending message is first broken up into many data packets, and each data packet is then transmitted to a receiving computer within the computer network. Each data packet is a separate entity on the communications media. After receipt within the network, each data packet is then stored in a buffer memory residing on a network adaptor, and finally, all of the data packets within the message are forwarded to a system memory within the receiving computer. This kind of network adaptor is commonly referred to as a "packet-based" adaptor or a stored-and-forward adaptor because data packets are first stored and then forwarded to the system memory by the network adaptor.
Generally, a packet-based adaptor requires a large amount of memory in order to buffer all the incoming data packets. This is especially true when the packet-based adaptor has to support a high-speed network link. A packet-based adaptor also requires an embedded controller with microcode or, alternately, some sophisticated hardware logic for managing the on-board buffer memory. Needless to say, the design complexity for such packet-based adaptor is very high, which translates into long development time and high manufacturing cost.
In addition to high design complexity, performance, such as adaptor latency, is also a big concern for packet-based adaptors. The temporary storage of packets in the buffer memory and the subsequent forwarding of packets to the system memory take time. When utilizing an embedded controller, which is commonly found in most packet-based adaptors, the execution of microcode could introduce additional latency (typically in the range of several hundred microseconds) to the processing of data packets. Because of the microcode execution and other overhead, the response time of a packet-based adaptor may be much longer than expected.
Furthermore, a packet-based adaptor also lacks flexibility and expandability. The buffer memory on the packet-based adaptor is dedicated only to that particular adaptor, hence, even when the network link is idle, no other process in the computer can take advantage of the on-board buffer memory. Also, in order to support virtual circuits, the required memory could be beyond what is presently capable within a typical packet-based adaptor. This is especially true for Asynchronous Transfer Mode (ATM) that is typically utilized in a high-end server environment, in which a large number of virtual circuits are required.
An alternative to the packet-based adaptor design is a cut-through (or pass-through) architecture. Under this architecture, the data packet receiving path is directly transferred from the network to the system memory via a speed-matching First-In-First-Out (FIFO) buffer to adapt to variations of the bus acquisition time and the speed mismatch between the network and the system bus. When applying the cut-through architecture, such adaptor can be called a "cell-based" adaptor because data is forwarded in one cell, and not packet, at a time. Without the requirement of storing-and-forwarding, the cell-based adaptor can eliminate the buffer memory and the necessity of an embedded controller. Thus, a cell-based adaptor has a much simpler architecture with minimal design complexity, which translates to lower manufacturing costs and less development time.
In addition, a cell-based adaptor also provides better flexibility and expandability over a packet-based counterpart. This is because the number of virtual circuits that can be supported by an adaptor is no longer restricted by the available local memory on the adaptor. In fact, the number of virtual circuits can grow as long as the system memory in the receiving computer can support such growth. Further, the performance of the cell-based adaptor, based on adaptor latency, is significantly better than that of the packet-based adaptor. This is due to the fact that the required latency for a packet-based adaptor to copy data in and out of the buffer memory is totally eliminated. The adaptor latency is further reduced by eliminating the need for managing a buffer memory. In sum, a cell-based adaptor has a superior latency performance, a lower design complexity, a lower development cost, a lower bill material cost, and still provides the flexibility and expandability for supporting many virtual circuits. In a client environment and lightly loaded low-end server environment, the low-cost, high-performance cell-based adaptor is an excellent choice.
However, a cell-based adaptor also poses some problems with respect to the overall system performance, especially for the high-end servers that need to support heavy I/O activities. A cell-based adaptor transfers data from a 48-byte Asynchronous Transfer Mode (ATM) cell to the system memory through the I/O bus and the system bus one at a time. Bursting data at a relatively small size of 48-byte could consume excessive bus bandwidth because a fixed bus protocol overhead will be incurred every time data is transferred. Also, the system memory in a high-end computer system is usually being accessed at a 32-byte or 64-byte segment at a time. Writing data that is not 32-byte or 64-byte aligned within such computer system would require a read-modified-write operation to be performed in order to prevent any data corruption. Thus, valuable memory bandwidth could be wasted because of this requirement of a read-modified-write operation for every transmission of 48-byte ATM cells to the system memory.
Much severe system performance degradation, however, comes from the high possibility of cell-dropping whenever the I/O bus cannot be acquired on time. A cell-based adaptor could transfer an ATM cell only if it can acquire the I/O bus. In a heavily equipped computer system, the cell-based adaptor could wait a long time (in the range of tens of microseconds) before the I/O bus is available. Because only one ATM cell within the FIFO buffer can be freed up every time the I/O bus is acquired, the FIFO buffer could be completely full in a short time if the ATM cells keep arriving from the high-speed computer network while the I/O bus can be acquired only every once in a while. When the FIFO buffer becomes full, the next arriving ATM cell will be dropped. A data packet with dropped cell(s) will be retransmitted by the sending computer when the error is detected by the upper-layer protocol. Needless to say, the recovery of dropped cells could consume system resources and would impact the overall system throughput as well as response time. When the cell-dropping rate is high, which is highly probable in a busy server environment, the system performance could be degraded significantly. Consequently, it would be desirable to provide a network adaptor for receiving and processing ATM cells in a more efficient manner within a computer network.